1. Field of the Invention
The present invention relates to a multiprocessor and particularly to a multiprocessor system, for example, a master slave system which ensures effective operation of different kinds of slave operation processing devices.
2. Description of the Prior Art
Various attempts have been made in conventional multiprocessor systems in order to improve performance as a whole by enhancing the parallel processing function. However, such attempts have encountered problems in the logic for assigning the processing to a plurality of operation processors, namely, for example, in the control systems for priority control and equal distribution of load.
As one example in the prior art of such parallel processing system for solving the problem described above, the distributional data transfer control system for parallel processor architecture indicated in the Japanese Patent Laid Open No. 57-172455 is known. The block diagram of such prior art system is shown in FIG. 1. This system distributes data to a plurality of operation processors. In FIG. 1, reference numeral 1 denotes the main bus; 2 denotes a control processor (master operation processing unit); 3, 3a-3c denote bus interface units; 4 denotes a resource controller; 5 denotes a main memory; 6, 6a-6c denote local memories and 7a-7c denote operation processors (slave operation processing units).
The conventional multiprocessor is constituted as described above and the system control is carried out by the control processor 2 and the main memory 5 where programs and data are stored.
First, for the execution of a program, the control processor 2 reads a program from the main memory 5 through the resource controller 4, main bus 1 and bus interface unit 3 for main memory 5 and recognizes the contents to be processed. In this case, actual processing operations are carried out by the operation processors 7a-7c. Therefore, in order to attain the maximum processing effect, the operations of bus interface units 3a-3c and local memories 6a-6c corresponding to respective operation units 7a-7c are preset in accordance with program. Thereafter, the control processor 2 decodes the program and reads required processing data from the main memory 5 and then supplies the control data required for processing and processing data to the pertinent operation processors 7a-7c of the operation processor 7 through the main bus 1. In this case, the operation processor among those 7a-7c for receiving each processing is predetermined by the operation and the parallel operations are carried with the maximum efficiency.
In the above conventional multiprocessor system, constitution is so established that the slave operation processing unit to be used for operations is predetermined. Therefore, it is necessary to preset the response of each bus interface unit and local memory in accordance with the control contents to be processed by the master operation processing unit. Moreover, if any of the operation processors in the slave operation processing unit fails, recalculation or reset of response is required. Further, such conventional multiprocessor system has a disadvantage that such calculation procedures and algorithms are complicated.